Not Applicable.
Not Applicable.
1. Field of the Invention
The present invention relates generally to digital-to-analog (D/A) converters. More particularly, the present invention relates to D/A converters taught herein that eliminate holes in output voltages by intentionally-placed downward steps in output voltages, thereby producing nonlinear output voltages. nonlinear digital-to-analog (D/A) converters for use in phase-locked oscillators, and in learning systems such as adaptive frequency-hopping oscillators.
2. Description of the Related Art
Digital-to-analog converters have found various uses in electronic devices. One use that has gained importance is D/A conversion of digitally-stored channelizing information to analog channelizing voltages used in frequency-hopping oscillators.
In frequency-hopping oscillators, it is sometimes advantageous to store channelizing information in digital form for a plurality of channelized frequencies, to subsequently recall digitally-stored channelizing information for one of the channelized frequencies, to D/A convert the recalled digital information for that one channel into a channelizing voltage, and to drive an output of frequency of a voltage controlled oscillator (VCO) approximately to phase lock for that one channelized frequency in response to that channelizing voltage.
Clark et al., U.S. Pat. No. 5,703,587, issued Dec. 30, 1997, use three 6-bit D/A converters and decoding logic, such as first and second exclusive OR gates, to convert sixteen bits of digital information.
Their D/A converter produces dual addresses by making the binary weight of the most significant bit of a lower-bits D/A converter the same as the binary weight of the least significant bit of a higher-bits D/A converter.
Noguchi, U.S. Pat. No. 5,914,682, issued Jun. 22, 1999, also produces dual addresses in the output voltage, but without the necessity of providing a greater number of bits than the binary number to be D/A converted, and also without the exclusive OR logic of Clark et al. Instead, Noguchi uses a resistor to proportion output voltages of an upper-bits D/A converter circuit and a lower-bits D/A converter.
Frequency-hopping transmitters are capable of transmitting radio frequencies on successive ones of a plurality of individual output frequencies with the output frequencies chosen in accordance with a code for a particular day or period.
Since the transmitted information remains on a given frequency for a matter of seconds, or microseconds, and since the order of selection of frequencies can be changed rapidly and precisely, information can be successfully encoded by the use of frequency-hopping transmitters.
As an example, when used to transmit video signals, a frequency-hopping transmitter could transmit each successive scan line at a different frequency.
The individual output frequencies are called channels, and the process of dividing a range of frequencies into channels is called channelizing. Each channelized frequency is produced by applying a selective voltage to a voltage-controlled oscillator (VCO), and the selective voltages that will drive the voltage-controlled oscillator to the channelized frequencies are called channelizing voltages.
Frequency-hopping oscillators can be designed to learn channelizing voltages for a particular voltage-controlled oscillator, to correct for errors of proportionality and nonlinearity of analog components, and to correct for temperature-caused drift of analog components. Learning systems are sometimes called adaptive systems or adaptive learning systems.
Charavit et al., in U.S. Pat. No. 4,511,858, issued Apr. 16, 1985, teaches embodiments of phase-locked oscillators that use analog integrators. Their phase-locked oscillators are adaptive in that channelizing voltages are stored, recalled, corrected through a phase-locked loop, and placed again in storage.
Hulbert et al., in U.S. Pat. No. 4,810,974, issued Mar. 7, 1989, teaches algebraically summing UP/DOWN signals in a counter which has therein previously stored channelizing information that has been recalled from a random access memory (RAM), correcting the channelizing information for temperature drift, one bit at a time, while driving the output frequency with channelizing information that is held in a latch. That is, corrected channelizing information is developed by counting and subsequently storing in a RAM for use the next time the same frequency is accessed.
A frequency-hopping transmitter is a transmitter that utilizes a frequency-hopping oscillator. In like manner, a frequency-hopping receiver is a receiver that utilizes a frequency-hopping oscillator. A frequency-hopping oscillator is a phase-locked oscillator that is channelized and whose channelized frequencies can be accessed rapidly in response to a predetermined program.
Phase-locked oscillators are used in transmitters for producing an output frequency that is crystal referenced, for demodulating frequency-modulated signals in radio receivers, to achieve frequency-deviation compression in frequency-modulated and phase-modulated receivers, and in various devices in which both rapid change to selected frequencies and precise frequency control are critical.
The use of phase-locked oscillators to achieve frequency-deviation compression in radio receivers is taught by Lautzenhiser in U.S. Pat. No. 5,091,706, issued Feb. 25, 1992; in U.S. Pat. No. 5,497,509, issued Mar. 5, 1996; and in U.S. Pat. No. 5,802,462, issued Sep. 1, 1998.
Phase-locked oscillators can be ac modulated, dc modulated, or both, as taught by Lautzenhiser in U.S. Pat. No. 5,091,706; in U.S. Pat. No. 5,097,230, issued Mar. 17, 1992; and in U.S. Pat. No. 5,311,152, issued May 10, 1994. In addition, phase-locked oscillators can be channelized as also taught by the aforesaid Lautzenhiser patents. Frequency-hopping oscillators may be ac and/or dc modulated using principles taught in the aforesaid Lautzenhiser patents.
In phase-locked oscillators, both a forward path and a feedback path are connected to a crystal-controlled reference oscillator by a comparing device. Phase lock is achieved when a feedback frequency from a voltage-controlled oscillator equals the frequency of the reference oscillator.
Channelization of phase-locked oscillators is achieved by channelizing the feedback path. The feedback path is channelized by dividing frequencies in the feedback path by N, as shown herein, by any of the ways taught by Lautzenhiser in the aforesaid patents, by partial N manipulation, or by nearly any other method that is conceivable.
Since channelization of the feedback path is dependent only upon the time required to divide the frequency in the feedback path by a different number, if a channelization voltage is simultaneously applied to the VCO, channelization is extremely rapid.
AC modulation of the forward path, at frequencies above the loop frequency, may be achieved by applying an analog voltage, or modulating voltage, to the VCO via a modulation resistor, as taught in the aforesaid Lautzenhiser patents, or by any other suitable means.
DC modulation of the feedback path may be achieved by digital manipulation of pulses in the feedback path, as taught by Lautzenhiser in the aforesaid patents, or by any other suitable means.
In phase-locked oscillators, an error signal is produced by a difference in a feedback frequency to a reference frequency. This error signal may be integrated by analog or digital circuitry.
In phase-locked oscillators that use an analog integrator, the error signal is time integrated. This time-integrated error signal, which is a voltage, is applied to the VCO during the integration process. The error signal disappears and integration stops when phase lock is achieved.
In phase-locked oscillators that use a digital integrator, the error signal is integrated by summing clock-timed UP, DOWN, and/or ZERO error signals. D/A conversion changes the digitally integrated error signal into a voltage which is applied to the VCO during the integration process. The error signal disappears and integration stops when phase lock is achieved.
Digital-to-analog converters of the present invention provide digital-to-analog (D/A) conversion without incurring errors that are commonly called xe2x80x9cholesxe2x80x9d, even when constructed using resistors that are far from being precise in their resistances. A xe2x80x9cholexe2x80x9d in a D/A converter is an output voltage that cannot be produced by any digital input. That is, one digital number will produce a voltage that is too low, and the next higher digital number will produce a voltage that is too high.
Not only do the digital-to-analog converters of the present invention eliminate holes, but, as a result, they also produce outputs that are not linearly proportional to digital inputs. Thus, the name, nonlinear D/A converters.
When the D/A converters of the present invention are used with learning systems, such as frequency-hopping oscillators that are described herein, the learning system adaptively corrects for the nonlinearities of the D/A converter. Thus, the nonlinearities do not degrade the performance of the system. Instead, since holes are eliminated, the accuracy and performance of the system is enhanced.
The frequency-hopping oscillators of the present invention include adaptive circuitry with learning and recalling functions, thereby providing frequency-hopping oscillators in which an output frequency of a VCO can be channelized without waiting for phase locking.
The method of the present invention includes generating UP/DOWN signals by phase detecting, decoding the UP/DOWN signals into increment/decrement signals, recalling previously stored channelizing information, parallel adding a single increment/decrement pulse to the recalled channelizing information in accordance with a sign (+1, 0, xe2x88x921) of the increment/decrement signal, and storing the corrected channelizing information in the RAM.
The method of the present invention further includes recalling the corrected channelizing information, repeating the parallel adding, storing, and recalling steps at a clock frequency to generate channelizing information that is progressively corrected, stored, and recalled, one increment/decrement pulse at a time, at the clock frequency.
The method of the present invention still further includes using the repeatedly recalled channelizing information, that is being corrected one increment/decrement pulse at a time at the clock frequency, to drive the output frequency progressively closer to phase lock substantially simultaneous with the parallel adding, storing, and recalling steps.
Therefore, the method of the present invention eliminates storing or latching steps, and therefore eliminates both the complexity in apparatus and the time that is required to perform housekeeping steps.
As shown and described herein, channelizing information, and/or frequency-correction information, is developed and stored that, when recalled will drive the output frequency to the desired channel almost instantly, and with very little deviation from frequencies that would phase lock for the respective channels.
The channelizing information compensates for errors in proportionality and linearity of such components as a D/A converter, an analog combiner/ offsetter, resistor values, and/or a VCO. Subsequent return to the same channelized frequency results in automatic correction for temperature drift of various components that may have occurred since the channel was last accessed.
The various embodiments include a digital integrator and special circuitry that mimics analog circuitry. That is, they each include circuitry that provides digital lead compensation, thereby providing loop stability for the digital integrators, even as analog integrators use a lead resistor in series with an integrating capacitor to achieve lead compensation and loop stability.
In first and second embodiments, lead compensation is achieved by analog summation of a channelizing voltage and a lead-compensating voltage. In a third embodiment, lead compensation is achieved by digital summation of digitized channelizing information and a digital lead-compensation signal.
Whereas the primary design objective of prior-art D/A converters has been to produce output voltages that increase linearly in response to increases in binary-coded inputs, the improved D/A converters of the present invention produce analog outputs that can be characterized as being intentionally nonlinear.
Whereas prior-art D/A converters provide analog outputs in which each higher bit hopefully produces a voltage that is exactly twice as high as the next lower bit, the D/A converters of the present invention can be characterized as producing analog outputs of a plurality of higher bits that are less than twice the analog output of each of a plurality of respective lower bits, irrespective of component variables.
The improved D/A converters of the present invention also can be characterized as producing analog outputs by a plurality of higher bits that are less than the sum of the outputs of all respective lower bits, irrespective of component variables.
The improved D/A converters of the present invention also can be characterized as producing analog outputs in response to a plurality of predetermined numerical inputs that are higher than the analog outputs produced by respective ones of next higher numerical inputs, irrespective of component variables.
The improved D/A converters of the present invention can be characterized as producing analog outputs with a plurality of downward steps, one for each increase in numerical input for a plurality of higher bits. That is, in a D/A converter of the present invention, if four bits are designed to produce downward steps, each of their fifteen numerical inputs would produce downward steps, irrespective of component variables.
Further, the improved D/A converters of the present invention can be characterized as having a plurality of dual addresses, irrespective of component variables. A D/A converter has dual addresses if substantially equal output voltages can be produced in response to two different digital inputs.
Still further, the improved D/A converters of the present invention can be characterized as being without holes, irrespective of component variables. By definition, a D/A converter has a hole if an increase by one in a digital input produces an increase in a voltage output that is at least twice as high as a normal increase in the output voltage when the digital input is increased by one. That is, a hole occurs when the output voltage increases twice as much as the output voltage for the least significant bit (lsb).
If a D/A converter has a hole in its output voltage, one digital input may produce an analog output that is too low to satisfy a need, such as phase locking, and the next higher digital input may produce an analog output that is too high to satisfy a need, such as phase locking.
For instance, if an increase in a numerical input of 1 produced a voltage step significantly higher than an average, or nominal, voltage step, the hole would reduce the effective resolution of the D/A converter.
Holes are caused by accumulative errors in resistances in D/A converters. While 12-bit D/A converters are practical and relatively economical, it is difficult and expensive to prevent holes in D/A converters with a larger number of bits because of the larger number of resistor tolerances and the random accumulation of the resistor tolerances.
That is, in prior-art linear D/A converters, by random selection of resistors, resistor tolerances cause both holes, dual addresses, and resultant nonlinearities to occur erratically with respect to one or more bits, and every effort has been made to eliminate these characteristics.
In contrast, in the present invention, holes are absolutely abolished in any of the bits that are designed to function according to the present invention, dual addresses with respect to a plurality of higher bits are included in at least a plurality of higher bits, and the dual addresses are designed sufficiently large that variations in resistances of the various components can never eliminate any of the dual addresses nor interject a hole in the place of any dual address.
The nonlinear D/A converters of the present invention allow lower cost resistors to be used, and allow a larger number of bits to be processed, even when low cost resistors are used.
Therefore, the present invention includes a nonlinear D/A converter that excels over prior-art D/A converters in both performance and cost when used in phase-locked oscillators, and in learning systems such as adaptive frequency-hopping oscillators.
In summary, in frequency-hopping oscillators of the present invention channelizing information and/or frequency-correction information is generated as increment/decrement pulses, the recalled channelizing information is corrected as an algebraic function of the increment/decrement pulses and at a clock frequency, the corrected channelizing information is used to drive the output frequency progressively closer to phase lock, and the recalling, correcting, driving, and storing steps are repeatedly repeated at the clock frequency before changing to another channel.
When phase lock is achieved, the generating of increment/decrement pulses ceases except as required to correct for drift, the accumulative summed values in the RAM become channelizing information, which, when recalled, will drive the output frequency to approximate phase lock for a selected channel in less than a microsecond.
In a first aspect of the present invention, a method for converting binary-coded inputs into an output voltage that varies as a function of bits of the binary-coded input comprises: summing output voltages of the bits; making an output voltage of each of a plurality of adjacent bits less than twice an output voltage of each respective next-lower bit; and making the less-than-twice relationships sufficient to prevent component tolerances from obliterating any of the less-than-twice relationships.
In a second aspect of the present invention, a digital-to-analog converter comprises: a plurality of series-connected ladder resistors; a plurality of bit resistors being connected to the ladder resistors; and the bit resistors have resistances that are more than twice as large as resistances of the ladder resistors.
In a third aspect of the present invention, a method for converting N bits of digital information into an output voltage comprises: series connecting a plurality of ladder resistors; connecting a plurality of bit resistors to the ladder resistors; making an output voltage of each of a plurality of adjacent ones of the bit resistors less than twice as large as an output voltage of a respective next-lower one of the bit resistors; and making the less-than-twice relationships sufficient to prevent resistor tolerances from obliterating any of the less-than-twice relationships.
In a fourth aspect of the present invention, in a digital-to-analog converter that converts N bits of digital information into an output voltage, the improvement which comprises: means for making an output voltage of each of a plurality of adjacent ones of the bits less than twice as large as an output voltage of each respective next-lower bit; and the less-than-twice relationships are sufficient to prevent resistor tolerances from obliterating any of the less-than-twice relationships.
In a fifth aspect of the present invention, a digital-to-analog converter for converting N bits of digital information into output voltages comprises: a first digital-to-analog converter portion for converting lower ones of the bits; a second digital-to-analog converter portion for converting higher ones of the bits; a first resistor connecting the first digital-to-analog converter portion to an output; a second resistor connecting the second digital-to-analog converter portion to the output; a third resistor connecting the output to an electrical ground; and resistances of the resistors are proportioned to make an output voltage of a plurality of highest bits less than a maximum output voltage of all of the respective lower bits, irrespective of resistor tolerances.